Master of Technology (Electronic Circuits and System Design), Bachelor of Technology (Electronics and Communication Engineering)
Electronic Circuits and System Design, Neuromorphic Circuits, Memristor based Circuits
4/1076, Dayar e Raoof, Civil Lines, Aligarh
Time table odd semester (Session 21-22)Time table even semester (Session 20-21)
Ms. Juhi Faridi received her B. Tech.(Electronics and Communication engineering) and M. Tech. (Electronic circuits and system design) degrees from the Department of Electronics Engineering, Aligarh Muslim University, Aligarh, India, in 2014 and 2017, respectively. She has worked as Research Assistant at Advanced computing laboratories in IIIT- Delhi, India. Presently she is employed as a Guest Faculty in Electronics Engineering Section at University Women's Polytechnic, AMU, Aligarh from January 2019 to date. She has published book chapters with Springer and has papers in IEEE Transactions on Circuits and System. She is GATE qualified and has an overall IELTS band 7. Her areas of interest include Electronics Circuit Design; Memristors based circuits and memristors in neuromorphic computing systems.
- Memristor-Based Tunable Analog Filter for Physiological Signal Acquisition for Electrooculography In this paper we demonstrate that Memristors can be used in conjunction with CMOS to implement a continuous-time tunable analog bandpass filter for use in the area of biomedical signal acquisition. The idea here is to implement a single band pass filter which can provide frequency tuning between EEG, EOG and ECG signals. Frequency tuning is achieved by varying the resistance of the Memristor (Memristance). The proposed circuit promises lower power dissipation and smaller-sized implementations than CMOS counterparts. This circuit is capable of filtering out biomedical signals (specifically Electrooculography (EOG) signals) and the same is demonstrated for the frequency range of 6–16 Hz. The power consumption of the band pass filter designed was found to be 127 nW at 0.25 V supply. The HSPICE simulation results were found in accordance to the qualitative discussion.
- Memristor: A Promising Candidate for Neural Circuits in Neuromorphic Computing Systems Technology has led to an evolution of an intelligent era. Neural networks, having the computational power and learning ability similar to the brain is one of the New AI technologies. Neuromorphic computing system (NCS) consists of the synaptic device, neuronal circuit, and neuromorphic architecture.This literature is a step in the direction where we describe the various Key findings about memristors and its analog and digital circuits implemented over the years which can be further utilized in implementing the neuronal circuits in the NCS.
- A Neuromorphic Majority Function Circuit with O (n) Area Complexity in 180 nm CMOS. An artificial neuron with a step activation function is first designed and verified. Thereafter, a synaptic weight generation circuitry is designed to provide a suitable sum current to the activation function neuron to achieve the task of majority function generation for digital logic inputs. HSPICE simulations are performed to verify the proposed theoretical framework, with the proposed network correctly yielding the appropriate low or high digital logic state corresponding to the input combinations applied. Superiority of the proposed circuit in terms of transistor area required is also demonstrated. The transistor count increase linearly with the number of variables in the case of the proposed circuit; whereas for conventional static CMOS implementations an exponential increase in transistor count is exhibited.
- "Partial-LUT Designs for Low-Complexity Realization of DA-based BLMS Adaptive Filter" This brief presents two-optimized partial look-up table (LUT) designs for low-complexity realization of distributed arithmetic (DA) based block least-mean-square (BLMS) adaptive filter (ADF). These are based on the partial add-store (PAS) and partial store-add (PSA) methods. A novel optimization scheme is presented which exploits the redundancies between the partial inner-products with sliding-window of input-block.