![photo](https://api.amu.ac.in/storage/images/empphoto/10079933-1717513726.jpg)
- DEPARTMENT_STAFF.QUALIFICATION
M Tech, B Tech, PhD
- DEPARTMENT_STAFF.DESIGNATION
Guest Faculty
- DEPARTMENT_STAFF.THRUST_AREA
Low power Energy-Efficient VLSI circuit and system design • FPGA, Hardware Implementation, Spintronics circuits • H/w security • Approximate computing • Binary/Ternary circuits • Digital/Analog Integrated circuits
- DEPARTMENT_STAFF.ADDRESS
University Women's Polytechnic, AMU. Aligarh
- DEPARTMENT_STAFF.MOBILE
7091255118
- DEPARTMENT_STAFF.EMAIL
mshussain@zhcet.ac.in
- DEPARTMENT_STAFF.TIME_TABLE
Mohd Shahbaz Hussain is working as Guest Faculty in the Electronics Engineering Section at the University Women's Polytechnic, AMU, Aligarh. He is GATE-qualified. He has published 3 research articles in SCI-indexed journals. In addition, he has published 1 Book Chapter and 6 papers at reputed conferences. He is pursuing PhD in the Department of Electronics Engineering (ELED) at Aligarh Muslim University, India.
Mr. Hussain's research initiatives and vision are primarily focused on designing energy-efficient circuits and approximate adder circuits for image and biomedical signal processing. His research interest lies in exploring the design of energy-efficient circuits. He demonstrates a remarkable proficiency in digital circuit-system design, nano-electronics, and designing and simulating with various tools such as Cadence Virtuoso, Cadence Encounter, FPGA Hardware implementation, Vivado and Hspice.
- M Hasan, Md Shahbaz Hussain, Mainul Hossain, Mohd Hasan, Hasan U. Zaman, and Sharnali Islam. "A high-speed and scalable XOR-XNOR-based hybrid full adder design." Computers & Electrical Engineering 93 (2021): 107200.
- Shahbaz Hussain, et al. "A high performance full swing 1 bit hybrid full adder cell." IET Circuits, Devices & Systems, 16(3), 210-217.(2021).
- A High-Performance Hybrid Full Adder Circuit MS Hussain, J Kandpal, M Hasan, M Muqeem - IEEE 9th Uttar Pradesh Section International …, 2022
- Implementation of Energy Efficient Full Adder for Arithmetic Application M Shahbaz Hussain, J Kandpal, M Hasan, K Guha - … Conference on Micro/Nanoelectronics Devices, Circuits …, 2023
- An Approximate Ternary Full Adder using Carbon nanotube field effect transistors A Malik, MS Hussain, M Hasan - 5th International Conference on Multimedia …, 2022
- A Hybrid FA for High Performance Arithmetic Application J Kandpal, R Gowari, VP Dubey, MS Hussain, J Joshi… - International Conference on Device Intelligence …, 2023
- Designing a Socially Intelligent System by Cognitive Modeling of Human-Environment Interaction S Anwar, A Alam, MS Hussain - Smart Data Intelligence: Proceedings of ICSMDI 2022,