DEPARTMENT.FACULTY
- DEPARTMENT_STAFF.QUALIFICATION
Ph.D (University of Edinburgh, UK), M.Tech. (IIT, Delhi)
- DEPARTMENT_STAFF.DESIGNATION
Professor
- DEPARTMENT_STAFF.THRUST_AREA
VLSI Design, Nanoelectronics, Embedded System
- DEPARTMENT_STAFF.ADDRESS
Wadie Ismail, Dhorra, Aligarh, India
- DEPARTMENT_STAFF.MOBILE
9897790043
- DEPARTMENT_STAFF.EMAIL
mohd.hasan@amu.ac.in
- DEPARTMENT_STAFF.TIME_TABLE
Prof. Hasan has been working as a full Professor since March, 2005. He served as Chairman (HoD) of the Department from 12 Oct., 2015 to 11 Oct., 2018. He completed his PhD from the University of Edinburgh, UK on a Commonwealth Scholarship in the area of "Low Power Architectures for Signal Processing and Communications". He also worked as a Visiting Researcher on his own Royal Academy of Engineering, UK funded project on "Low Power FPGA' in the same University. He has published 178 papers in refereed journals and conferences with 2335 citations, h-index=26 and i10 index=57. This also includes eighteen IEEE Transactions/Journals and 56 Scopus indexed journal publications. He received "Paper of the Year Award" by the Editors of the prestigious International ETRI Journal for his paper entitled "High Performance Low power FFT cores" along with best International conference paper awards. He has supervised ten PhDs and currently supervising two more along with many Master level Dissertations. He has delivered several keynote addresses and invited talks in Conferences and Workshops. He has two awarded patents on "Low Power and Robust SRAM" and "Binary content addressable memory based on MTJ for wide arrays", and two filed patents on the design of magnetic RAM (MRAM). His research interests are in VLSI Design, Nanoelectronics, Energy efficient architectures for AI/ML, Spintronics, Battery-less electronics, Variability aware design. He is also a Senior member of IEEE.
- Publications
1. Mohd. Tausif, Abhinandan Jain, Ekram Khan and Mohd. Hasan, “Memory-efficient architecture for FrWF-based DWT of high-resolution images for IoMT applications” Multimedia Tools and Applications, 5th January, 2021.
2. Mohd. Tausif, Ekram Khan, Mohd. Hasan and Martin Reisslein, “Lifting-Based Fractional Wavelet Filter: Energy-Efficient DWT Architecture for Low-Cost Wearable Sensors”, Advances in Multimedia Journal, Vol. 2020, 16 December, 2020.
3. Sayeed Ahmad, Syed Afzal Ahmad, Mohd Muqeem, Naushad Alam, Mohd Hasan, “TFET-Based Robust 7T SRAM Cell for Low Power Application”, ISI indexed IEEE Transactions on Electron Devices, Vol. 66 Issue 9, pp. 3834-3840, August, 2019
4. Mohd Tausif, Abhinandan Jain, Ekram Khan, Mohd Hasan, “Efficient Architectures of Fractional Wavelet Filter (FrWF) for Visual Sensors and Wearable Devices”, Scopus indexed IEEE Sensors (Early Access), July , 2019.
5. Mohd. Tausif, Ekram Khan, Mohd. Hasan, Martin Reisslien, “SMFrWF: Segmented Modified Fractional Wavelet Filter: Fast Low-Memory Discrete Wavelet Transform (DWT)” Scopus indexed IEEE Access, Vol.7, pp. 84448-84467, June 2019
6. Ahmed Shaban, Sayeed Ahmad, Naushad Alam, Mohd Hasan, “Compact and Low Power 11T-2MTJ Non-Volatile Ternary Content Addressable Memory Cell with High Sense Margin”, Scopus indexed Journal of Low Power Electronics, Vol. 15 (Issue 2) pp. 193-203, June 2019.
7. Mohd Tausif, Abhinandan Jain, Ekram Khan, Mohd Hasan, “Low Memory Architectures of Fractional Wavelet Filter for low-cost Visual Sensors and Wearable Devices”, Scopus indexed IEEE Sensors, pp. 1-4, Oct., 2018.
8. Sayeed Ahmad, Naushad Alam and Mohd. Hasan “Robust TFET SRAM cell for ultra-low power IoT applications”, Scopus indexed Elsevier’s AEU International Journal of Electronics and Communications, Vol. 89, pp. 70-76, May, 2018
9. Sayeed Ahmad, Belal Iqbal, Naushad Alam and Mohd. Hasan “Low Leakage Write-Enhanced Bit-Interleaving Robust SRAM Cell with BTI Reliability Analysis” ISI indexed IEEE Transactions on Device and Material Reliability, Vol. 18 no. 3, pp. 337-349, Sept. 2018.
10. Sayeed Ahmad, Naushad Alam, Mohd. Hasan, “Pseudo Differential Multi-Cell Upset Immune Robust SRAM Cell for Ultra-Low Power Applications”, Scopus indexed AEU International Journal of Electronics and Communications (Elsevier), Vol. 83, pp. 366-375, 2018.
11. S. Ahmad, M. K. Gupta, N. Alam, M. Hasan, “Low Leakage Single Bitline 9T (SB9T) Static Random Access Memory”, ISI indexed Elsevier’s Microelectronics Journal, Vol. 62, pages 1-11, 2017
12. Mohit K. Gupta and M. Hasan, “Self-Terminated Write Assist Technique for STT-RAM”, ISI indexed IEEE Transactions on Magnetics, Vol. 52 Issue 8, August, 2016.
13. Sayeed Ahmad, M.K. Gupta, Naushad Alam, M. Hasan, “Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell”, ISI indexed IEEE Transactions on VLSI Systems, vol. 24, no. 8, 2634-2642, August, 2016.
14. Yogendra Upadhyaya, Mohit K. Gupta, M. Hasan, S. Maheshwari, “High Density Magnetic Flash ADC using Domain Wall Motion and Pre-Charge Sense Amplifiers”, ISI indexed IEEE Transactions on Magnetic, Vol. 52, Issue 6, June 2016.
15. Mohit Kumar Gupta and M. Hasan, “A Low Power Robust Easily Cascaded PentaMTJ based Combinational and Sequential Circuits” ISI indexed IEEE Transactions on VLSI Systems, Vol. 24, Issue 1, pp. 218-222, Jan. 2016.
16. Mohit K. Gupta and M. Hasan, “Robust High speed Ternary Magnetic Content Addressable Memory” ISI indexed IEEE Transactions on Electron Devices, Vol. 62, Issue 4, pp. 1163-1169, April, 2015.
17. Mohit Kumar Gupta and M. Hasan, “Design of high speed energy efficient masking error immune PentaMTJ based TCAM” ISI indexed IEEE Transactions on Magnetics, Vol. 51, No. 2, 3400209, Feb., 2015.
18. M.A. Kafeel, S.D. Pable, M. Hasan, M.S. Alam, “Optimization and Characterization of CMOS for Ultra Low Power Applications”, Scopus indexed Journal of Nanotechnology, Volume 2015, Article ID 395090, 6 pages
19. S.D. Pable, Mohd. Hasan, S.A. Abbasi and A.R.M. Alamoud, “Interconnect optimization to enhance the performance of subthreshold circuits”, ISI indexed Elsevier’s Microelectronics Journal, Vol. (44), Issue (5), pp. 454-461, March 2013.
20. M. Ajmal Kafeel, M. Hasan,“Performance Evaluation of CNFET based Single-Ended 6T SRAM cell” SCI Indexed Wulfenia Journal Volume 20, Issue 7, July 2013, pages 364-383.
21. Ale Imran, Aminul Islam, M. Hasan and S.A. Abbasi, “Optimized Design of a 32nm CNFET based Low Power Ultra Wide band CCII”, ISI indexed IEEE Transactions on Nanotechnology, Vol. 11, Issue 6, pp. 1100-1109, Nov., 2012.
22. Aminul Islam and Mohd. Hasan, “Leakage Characterization of 10T SRAM Cell”, ISI indexed IEEE Transactions on Electron Devices, Vol. 59, Issue 3, pp. 631-638, March, 2012.
23. S.D. Pable and Mohd. Hasan, “Interconnect Design for Subthreshold Circuits”, ISI indexed IEEE Transactions on Nanotechnology, Vol. 11, Issue 3, pp. 633-639, May, 2012.
24. Aminul Islam and Mohd. Hasan, “A Technique to Mitigate Impact of Process Voltage and Temperature Variations on Design Metrics of SRAM Cell” ISI indexed Elsevier’s Microelectronics Reliability, Vol. 52, no. 2, pp. 405-411, February, 2012.
25. Aminul Islam and Mohd. Hasan, "Variability Aware Low Leakage Reliable SRAM Cell Design Technique, "ISI indexed Elsevier’s Microelectronics Reliability, Vol. 52, Issue 6, pp. 1247-1252, June, 2012.
26. Aminul Islam and Mohd. Hasan, “Variation Resilient Subthreshold SRAM Cell Design Technique," ISI indexed International Journal of Electronics, Vol. 99, No. 9, pp. 1223-1237, Sept. 2012.
27. S.D. Pable and Mohd. Hasan, “Ultra-low-power signaling challenges for subthreshold global interconnects”, ISI indexed Elsevier’s Integration, The VLSI Journal, Vol. 45, Issue 2, pp. 186-196, March, 2012.
28. S.D. Pable and Mohd. Hasan, “A Novel Robust FPGA Routing Switch Box Design for Ultra Low Power Applications”, ISI indexed International Journal of Electronics, Vol. 99, Issue 1, pp. 15-27, Sept. 2011, DOI: 10.1080/00207217. 2011.609977.
29. S.D. Pable and Mohd. Hasan, “Robustness comparison of emerging devices for portable applications,” Scopus indexed Journal of Nanomaterials, Volume 2012 (2012), Article ID 242459, 8 pages DOI:10.1155/2012/242459.
30. S.D. Pable and Mohd. Hasan, “High Speed Interconnect through Device Optimization for Subthreshold FPGA”, ISI indexed Elseviers’s Microelectronics Journal, Vol. 42, No. 3, pp. 545-552, Jan., 2011.
31. Aminul Islam, Mohd. Hasan, “Power optimized variation aware dual-threshold SRAM cell design technique”, Scopus indexed Nanotechnology, Science and Applications, Vol. 2011:4, pp. 25-33, Feb., 2011, DOI: 10.2147/NSA.S15719.
32. Fahad Ali Usmani and M. Hasan, " Carbon Nanotube Field Effect Transistors for High Performance Analog Applications: An Optimum Design Approach”, ISI indexed Elseviers’s Microelectronics Journal, Vol. 41, Number 7, pp. 395-402, July, 2010.
33. A.K. Kureshi and M. Hasan, "Analysis of CNT Bundle and its Comparison with Copper Interconnect for CMOS and CNFET Drivers," Scopus indexed Journal of Nanomaterials, Vol. 2009, Article ID 486979, 6 pages, 2009.
34. Kureshi A. K. and Mohd. Hasan, “DTMOS Based Low Power High Speed Interconnects for FPGA", Scopus
indexed Journal of Computers (Academy Publisher Finland), vol.4, No.10, pp.921-926, Oct. 2009.
35. A.K. Kureshi and M. Hasan, “Comparison of performance of Carbon nanotube FET and bulk CMOS based 6T SRAM cell in deep submicron”, ISI indexed Elsevier’s Microelectronics Journal, Vol. 40, No. 6, pp. 979-982, June 2009.
36. W. Han, A.T. Erdogan, T. Arslan and M. Hasan, ‘High performance low power FFT cores’, ISI indexed ETRI Journal, vol.30, no.3, pp. 451-460, June 2008. (Paper of the year 2008 award)
37. Hemendra Varshney, Sambhav Jain and Mohd. Hasan, ‘Energy efficient novel architectures for the lifting based Discrete Wavelet Transform’, ISI indexed IET Proceedings on Image Processing, Vol. 1, Issue 3, P305-310 September, 2007.
38. Syed Mohsin Reza Zaidi and M. Hasan, “An Energy Efficient Programmable Hardware Implementation of the Secure Hash 384 and 512 Algorithms” ISI indexed IETE Journal of Research, Vol. 53, No. 5, September-October, 2007.
39. M. Hasan, T. Arslan and J.S. Thompson, ‘Low power adaptive MC-CDMA transceiver architectures’, ISI indexed ETRI Journal, vol. 29, no. 1, pp. 79-88, Feb. 2007.
40. M. Hasan, T. Arslan and J.S. Thompson, ‘A low power architecture for a MC-CDMA receiver’, ISI indexed IETE Journal of Research, vol. 51 no. 6, pp. 459-464, November-December 2005.
41. Prabhat Arora, Manish Singhal, M. Hasan, S.A. Abbasi, ‘VHDL modeling and FPGA based implementation of a memory efficient Huffman decoder’, Scopus indexed IETE Technical review, vol. 21, No. 6, pp-371-377, November-December 2004.
42. M. Hasan and T. Arslan, ‘Implementation of low power FFT processor cores using a novel order based processing scheme’, IEE proceedings on Circuits, Devices and Systems, vol. 150, no. 3, pp. 149-154, June 2003.
43. A.T. Erdogan, M. Hasan and T.Arslan, ‘Algorithmic low power FIR cores’, ISI indexed IEE proceedings on Circuits, Devices and Systems, vol. 150, no. 3, pp. 155-160, June 2003.
44. M. Hasan, T. Arslan and John Thompson, ‘A Novel coefficient ordering based low power pipelined radix-4 FFT processor for wireless LAN applications’, ISI indexed IEEE Transactions on Consumer Electronics, vol. 49, no. 1, pp.128-134, February, 2003.
45. M. Hasan and T. Arslan, ‘Scheme for reducing size of the coefficient memory in FFT processor’, ISI indexed Electronic letters, Vol. 38, no. 4, pp.163-164, February, 2002.
46. M. Hasan and T. Arslan, ‘Coefficient memory addressing scheme for high performance FFT processors", ISI indexed Electronic Letters, Vol. 37, no. 22, pp.1322-1324, October, 2001.
47. M. Hasan, S. A. Abbasi, K. N. Khan and S. A. Faraz, ‘A Novel Design and FPGA Based Implementation of a Byte Wise CRC Code Generator Chip using VHDL’, Scopus indexed IETE (Institution of Electronics and Telecommunication Engineers) Technical Review, Vol. 15, no.6, p487 - 490, 1998.
48. M. Hasan, M. S. Imam, R. Sharma and S. A. Abbasi, ‘A Novel Design and FPGA Based Implementation of a Complex Synchronization Signal Generator for Television’, ISI indexed IEEE Transactions on Consumer Electronics, Vol. 43, no.4, p1143-1151, 1997.